Dual bit memory cells are known in the art. One such memory cell is the NROM (nitride read only memory) cell 10, shown in FIG. 1 to which reference is now made, which stores two bits 12 and 14 in a nitride based layer 16, such as an oxide-nitride-oxide (ONO) stack, sandwiched between a polysilicon word line 18 and a channel 20. Channel 20 is defined by buried bit line diffusions 22 on each side which are isolated from word line 18 by a thermally grown oxide layer 26, grown after bit lines 22 are implanted. During oxide growth, bit lines 22 may diffuse sideways, expanding from the implantation area.
NROM cells are described in many patents, for example in U.S. Pat. No. 6,649,972, assigned to the common assignees of the present invention, whose disclosure is incorporated herein. Where applicable, descriptions involving NROM are intended specifically to include related oxide-nitride technologies, including SONOS (Silicon-Oxide-Nitride-Oxide-Silicon), MNOS (Metal-Nitride-Oxide-Silicon), MONOS (Metal-Oxide-Nitride-Oxide-Silicon) and the like used for NVM devices. Further description of NROM and related technologies may be found at “Non Volatile Memory Technology”, 2005 published by Saifin Semiconductor and materials presented at and through http://siliconnexus.com, “Design Considerations in Scaled SONOS Nonvolatile Memory Devices” found at:
http://klabs.org/richcontent/MemoryContent/nvmt_symp/nvmts—2000/presentations/bu_white_sonos_lehigh_univ.pdf, “SONOS Nonvolatile Semiconductor Memories for Space and Military Applications” found at:
http://labs.org/richontent/MemoryContent/nvmt—000/papers/adams_d.pdf, “Philips Research—Technologies—Embedded Nonvolatile Memories” found at: http://research.philips.com/technologies/ics/nvmemories/index.html, and “Semiconductor Memory: Non-Volatile Memory (NVM)” found at: http://ece.nus.edu.sg/stfpage/elezhucx/myweb/NVM.pdf, all of which are incorporated by reference herein in their entirety.
As shown in FIG. 2, to which reference is now briefly made, NROM technology employs a virtual-ground array architecture with a dense crisscrossing of word lines 18 and bit lines 22. Word lines 18 and bit lines 22 optimally can allow a 4 F2 size cell, where F designates the minimum feature size of an element of the chip for the technology in which the array was constructed. For example, the feature size for a 65 nm technology is F=65 nm.
For NROM cells, the minimum length of a cell is 2 F, being the minimum length (1 F) of a bit line 22 plus the minimum length (1 F) of a spacing 23 between bit lines 22. The minimum width of a cell is also 2 F, being the minimum width (1 F) of a word line 18 plus the minimum width (1 F) of a spacing 19 between word lines 18. Thus, the theoretical minimum area of a cell is 4 F2.
It should be noted, that it is possible to create bit lines 22 of less than 1 F, but in such cases the length of associated spacing 23 must be increased by a corresponding amount, such that the total length of a bit line 22 and an associated spacing 23 must be at least 2 F. Similarly, it is possible to create word lines 18 of less than 1 F, but in such cases the width of associated spacing 19 must be increased by a corresponding amount, such that the total width of a word line 18 and an associated spacing 19 must be at least 2 F.
Unfortunately, most NROM technologies which use the more advanced processes of less than 170 nm (where F=0.17 μm) employ a larger cell, of 5-6 F2 due to the side diffusion of the bit lines which required a bit line spacing of about 1.6 F.
There exists a dual polysilicon process (DPP) for the NROM cell, where a first polysilicon layer is deposited and etched in columns between which bit lines 22 are implanted. Word lines 18 are then deposited as a second polysilicon layer, cutting the columns of the first polysilicon layer into islands between bit lines 22. Before creating the second polysilicon layer, bit line oxides are deposited between the first polysilicon columns, rather than grown as previously done. The result are bit line oxides that remain within the feature size of the polysilicon columns. In some DPP processes, spacers are created on the sides of the first polysilicon columns, which reduces the space for the bit lines. This enables the bit lines to be thinner than 1 F. For example, bit lines 22 might be 0.7 F while the columns between them might be 1.6 F. This produces a width of 2.3 F and a resultant cell area of 4.6 F2, which is closer to the theoretical minimum of 4 F2 than for prior processes, but still not there. Approaching the theoretical minimum is important as there is a constant push in industry to put more features into the same real estate.